CCD driver implemented on ZYNQ7000

Finally put the TCD1304 linear CCD driver onto my XC7Z020 board. The IP core provides an AXI-Lite interface for register access to adjust the CCD driving parameters in realtime. It also offers a high-speed AXI-Stream port for CCD reading output. Connecting the AXI-Stream port to an AXI-Data FIFO IP followed by a Xilinx VDMA IP, we can automatically save frames into a pre-allocated memory pool which act as a frame buffer. Thanks to the VDMA IP core, I can quickly get informed from the linux side when buffer is ready and get synced with the CCD driver.

Myir XC7Z020 board, connected to my home network through 1000Mbps ethernet.

TCD1304 linear CCD and a temporary LTC1865A 250ksps 16bit ADC with serial interface, I will replace it with AD7960 in future design.

Oscilloscope result: Red is ICG trigger, yellow is CCD buffered output.

 

ZYNQ 7000 : AXI4-Lite based MMCM dynamic configuration

Start my hardware project on Xilinx ZYNQ 7000 MPSoC device!

I have got a Z-turn board (designed by Myir Technology) equipped with XC7Z020 SoC chip.

To briefly introduce the ZYNQ devices, we can define it as a combination of FPGA and a dual-core ARM Cortex-A9 processor(also called hard core compared to soft core like MicroBlaze) with on-chip programmable interconnection. The internal connection make the data transfer easier and faster than the previous scheme that place an external ARM processor near a FPGA chip. In the ZYNQ scheme, they call the ARM part Processing System(PS), and the FPGA part Processing Logic(PL). Many convenient implementation of AXI4 bus is provided by Xilinx as IP cores. With the block design function in Vivado, we can quickly integrate our IP cores into the system. Also thanks to the powerful ARM core, we can run Linux operating systems on the PS and directly control all the hardware implementation on the PL.

In Xilinx devices, the clock can be generated by a module called Mixed-Mode Clock Manager(MMCM), which includes a PLL. This module have fractional multiplier and divider thus is quite versatile to meet any need for digital clock generation. Another good thing is that it can be dynamically reconfigured through a set of registers.

The MCMM_DRP is connected to the PS GP0 port through an AXI-interconnection module. I have allocated a small 4KB virtual space for the registers starting at 0x40000000(which is right after my 1GB DDR3 RAM). Because of the limited bandwidth of my Mini-DSO, I have put a 1/4096 clock divider at the output.

In the Linux side, I have two choices to make modifications on registers. The first way is to write a kernel driver that well handles the requests from user space and do the reconfiguration on registers. However, this is not so easy to implement. The another way is to use mmap to map the registers to a virtual address and modify that. This way is easy and can be done in the user space(root privilege is required, though), but not safe. As a simple test and our ‘Hello world!’ project to ZYNQ, I chose the second plan.

 

TCD1304 Verilog Driver for Spectrometer Project

Spend several hours to finish some verilog HDL code driving a TCD1304DG linear CCD from Toshiba. This work is intended for the CCD spectrometer project in the future.

The project will utilize a high precision 18bit SAR ADC (AD7960) to sample the CCD output at a very fast speed up to 5MSa/s. The code is written versatilely that many timing constraints can be directly reprogrammed through registers. When I finish the connection between this IP and the Zynq 7000 PS, it would be convenient to control the CCD sampling parameters from linux side.

The simulation result is shown below.

The 8th row: SH signal

The 9th row: ICG signal

The 10th row: MCLK signal for CCD

ccd_timing_test

FPGA based high speed real time data recorder

This project builds a FPGA controlled analog card that can transfer sampled analog data to computer through USB 2.0 interface. I have achieved over 30MB/s stable real time data recording using this device. Data are received by a libusb based python script and written into hard drive. So the recording length is totally limited by the free space of your hard drive.

This is the device itself.

Analog Device: AD8023 40MS/s 10bit ADC, Xilinx: Spartan-6 XC6SLX25 FPGA, Cypress: CY7C68013 USB 2.0 controller

fpga_usb_analog_card

A hertz level sine wave recorded by this device. The data file is 200MB in size and I use mmap to speed up the reading process and prevent memory overflow. I have tested to record for more than a minute, it did not lose any packet!fpga_analog_recorder