CCD driver implemented on ZYNQ7000

Finally put the TCD1304 linear CCD driver onto my XC7Z020 board. The IP core provides an AXI-Lite interface for register access to adjust the CCD driving parameters in realtime. It also offers a high-speed AXI-Stream port for CCD reading output. Connecting the AXI-Stream port to an AXI-Data FIFO IP followed by a Xilinx VDMA IP, we can automatically save frames into a pre-allocated memory pool which act as a frame buffer. Thanks to the VDMA IP core, I can quickly get informed from the linux side when buffer is ready and get synced with the CCD driver.

Myir XC7Z020 board, connected to my home network through 1000Mbps ethernet.

TCD1304 linear CCD and a temporary LTC1865A 250ksps 16bit ADC with serial interface, I will replace it with AD7960 in future design.

Oscilloscope result: Red is ICG trigger, yellow is CCD buffered output.

 

ZYNQ 7000 : AXI4-Lite based MMCM dynamic configuration

Start my hardware project on Xilinx ZYNQ 7000 MPSoC device!

I have got a Z-turn board (designed by Myir Technology) equipped with XC7Z020 SoC chip.

To briefly introduce the ZYNQ devices, we can define it as a combination of FPGA and a dual-core ARM Cortex-A9 processor(also called hard core compared to soft core like MicroBlaze) with on-chip programmable interconnection. The internal connection make the data transfer easier and faster than the previous scheme that place an external ARM processor near a FPGA chip. In the ZYNQ scheme, they call the ARM part Processing System(PS), and the FPGA part Processing Logic(PL). Many convenient implementation of AXI4 bus is provided by Xilinx as IP cores. With the block design function in Vivado, we can quickly integrate our IP cores into the system. Also thanks to the powerful ARM core, we can run Linux operating systems on the PS and directly control all the hardware implementation on the PL.

In Xilinx devices, the clock can be generated by a module called Mixed-Mode Clock Manager(MMCM), which includes a PLL. This module have fractional multiplier and divider thus is quite versatile to meet any need for digital clock generation. Another good thing is that it can be dynamically reconfigured through a set of registers.

The MCMM_DRP is connected to the PS GP0 port through an AXI-interconnection module. I have allocated a small 4KB virtual space for the registers starting at 0x40000000(which is right after my 1GB DDR3 RAM). Because of the limited bandwidth of my Mini-DSO, I have put a 1/4096 clock divider at the output.

In the Linux side, I have two choices to make modifications on registers. The first way is to write a kernel driver that well handles the requests from user space and do the reconfiguration on registers. However, this is not so easy to implement. The another way is to use mmap to map the registers to a virtual address and modify that. This way is easy and can be done in the user space(root privilege is required, though), but not safe. As a simple test and our ‘Hello world!’ project to ZYNQ, I chose the second plan.

 

Write a python application monitoring lasers!

Life is short, use python!

There are bunches of frameworks to support a graphical user interface (GUI) on your python application. I choose to use wxPython because I was familiar with that. I embed the graph generated by matplotlib into the GUI to give realtime updating of the data.

This application uses a HighFinesse wavelength meter monitoring a Rubidium locked laser and a commercial He-Ne laser. It can automatically record data into a file and calculate the deviation. A round-robin buffer is used to show short-term and long-term data.

short

long

deviation

viewdata

Noise of a current source

Precision current sources are critical electronics in atomic physics. They can serve as power supply for diode lasers or drive a coil to generate a precise magnetic field. We sometimes need to have the load grounded in experiments to prevent short-circuit on the conductive optical table. This demand is often achieved by using an instrumentation amplifier(INA). The current flow through a sensing resistor and the voltage drop on that resistor is sampled by INA and feedback to the output stage. We find AD8429 from Analog Devices a great INA choice for a bi-polar current source with the input noise density as low as 1nV/\sqrt{Hz}.

When facing with extremely noise sensitive application, we should have a second look at our design. In our old design, the Gain=1 is set without gain setting resistor attached. This seemed very convenient because we do not want gain drift. The mismatch of the temperature coefficient of the on-chip resistors and the external gain setting resistor will sure cause terrible gain drift. In fact, the total input referred noise of an INA should include the output noise part attenuated from the feedback network. The AD8429 has a very decent input noise density 1nV/\sqrt{Hz}, but a relative higher output noise density 45nV/\sqrt{Hz}. When the INA runs at Gain=1, the total input referred noise is dominated by the unattenuated output noise of the chip. The result is nearly  45nV/\sqrt{Hz} noise density on the input after RMS summing of the two kinds of noise!

An easy way to fix this is to increase the gain of the INA. In our configuration, a 200m\Omega current sensing resistor is used under the maximum current 5A(1V voltage drop). If we can amplifier that to 10V, which is still inside the rail of the INA, the output noise contribution will also be greatly reduced to 1/10. However, it is difficult to just place a resistor on that chip due to the temperature drift mentioned before. Instead, I find AD8228, which has a pair of internal matched gain setting resistors, providing Gain=10 and Gain=100 through simply opening or shorting the gain setting pins. For its fixed gain, the noise density of AD8228 referred in the datasheet includes the output noise contribution on the input noise. This means that the 15nV/\sqrt{Hz} should be the final input referred noise density of AD8228 under Gain=10 setting. Definitely much better than 45nV/\sqrt{Hz}!

TCD1304 Verilog Driver for Spectrometer Project

Spend several hours to finish some verilog HDL code driving a TCD1304DG linear CCD from Toshiba. This work is intended for the CCD spectrometer project in the future.

The project will utilize a high precision 18bit SAR ADC (AD7960) to sample the CCD output at a very fast speed up to 5MSa/s. The code is written versatilely that many timing constraints can be directly reprogrammed through registers. When I finish the connection between this IP and the Zynq 7000 PS, it would be convenient to control the CCD sampling parameters from linux side.

The simulation result is shown below.

The 8th row: SH signal

The 9th row: ICG signal

The 10th row: MCLK signal for CCD

ccd_timing_test