Laser Locked!

Finally lock my homemade diode laser onto the super stable cavity!

It is not that easy to do this because the cavity is a ULE cavity with finesse as high as 300,000. The line width of this little monster is as low as 5kHz, which is far below the typical ECDL bandwidth. (So the PDH dispersive signal we get from the oscilloscope is actually representing the line width of.our unlocked laser!) We also need to fine tune the loop filter and stabilize our modulators to get a stable lock.

The laser table. See our homemade ECDL (can be hermetic but we have not do that yet).ecdl_photo

The locking table. Mode matching, cavity, vacuum, etc. You can see the strong transmission light through the cavity after lock in the small monitor on the upper right corner of the photo.cavity_photo

Our homemade high speed photo detector. Powered by a LEMO connector with very soft silica cable. The shielding is done by CNC the copper box, which works really good that no interference from the modulator can be seen at the PD output in the spectrum analyzer down to -90dBm.pd_photo

Our all-homemade electronics!elec_photo

In order to further determine the actual line width, we need to setup another set of laser and measure the beat notes between the two lasers.

Our preliminary scheme is to collect the beat notes with a high speed photodetector and down covert it to kilohertz region using a mixer. The final result will be readout by a dynamic analyzer (SR785) and a frequency counter. The signal generator, dynamic analyzer and the frequency counter will all be synchronized to a rubidium frequency standard.

P.S. Our GIANT SR785 just arrived!

sr785

 

TCD1304 Verilog Driver for Spectrometer Project

Spend several hours to finish some verilog HDL code driving a TCD1304DG linear CCD from Toshiba. This work is intended for the CCD spectrometer project in the future.

The project will utilize a high precision 18bit SAR ADC (AD7960) to sample the CCD output at a very fast speed up to 5MSa/s. The code is written versatilely that many timing constraints can be directly reprogrammed through registers. When I finish the connection between this IP and the Zynq 7000 PS, it would be convenient to control the CCD sampling parameters from linux side.

The simulation result is shown below.

The 8th row: SH signal

The 9th row: ICG signal

The 10th row: MCLK signal for CCD

ccd_timing_test