Finally put the TCD1304 linear CCD driver onto my XC7Z020 board. The IP core provides an AXI-Lite interface for register access to adjust the CCD driving parameters in realtime. It also offers a high-speed AXI-Stream port for CCD reading output. Connecting the AXI-Stream port to an AXI-Data FIFO IP followed by a Xilinx VDMA IP, we can automatically save frames into a pre-allocated memory pool which act as a frame buffer. Thanks to the VDMA IP core, I can quickly get informed from the linux side when buffer is ready and get synced with the CCD driver.
Myir XC7Z020 board, connected to my home network through 1000Mbps ethernet.
Oscilloscope result: Red is ICG trigger, yellow is CCD buffered output.