Spend several hours to finish some verilog HDL code driving a TCD1304DG linear CCD from Toshiba. This work is intended for the CCD spectrometer project in the future.
The project will utilize a high precision 18bit SAR ADC (AD7960) to sample the CCD output at a very fast speed up to 5MSa/s. The code is written versatilely that many timing constraints can be directly reprogrammed through registers. When I finish the connection between this IP and the Zynq 7000 PS, it would be convenient to control the CCD sampling parameters from linux side.
The simulation result is shown below.
The 8th row: SH signal
The 9th row: ICG signal
The 10th row: MCLK signal for CCD